Leakage power estimation

ABSTRACT

Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values ( 108 ) and one or more voltage values ( 110 ) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.

BACKGROUND

The present disclosure generally relates to the field of electronics.More particularly, an embodiment of the invention relates to leakagepower estimation in an integrated circuit (IC) device.

Power consumption, both dynamic and leakage, is one of the majorconcerns in IC design. In particular, sub-threshold leakage (or leakagepower) may be growing with each successive design generation. Forexample, as supply voltage is lowered (e.g., to reduce dynamic powerconsumption), threshold voltage may also be lowered (e.g., to maintainlow gate delay or high frequency). However, lowering the thresholdvoltage may affect leakage power nonlinearly.

In some implementations, leakage power may be assumed to have a constantvalue during run-time. However, leakage power may vary during run-time,for example, due to changes in temperature, supply voltage, or thresholdvoltage. Accordingly, power management techniques may be less accuratewithout knowledge of leakage power.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is provided with reference to the accompanyingfigures. In the figures, the left-most digit(s) of a reference numberidentifies the figure in which the reference number first appears. Theuse of the same reference numbers in different figures indicates similaror identical items.

FIGS. 1, 5, and 6 illustrate block diagrams of computing systems inaccordance with various embodiments of the invention.

FIGS. 2A and 2B illustrate block diagrams of portions of leakage powerestimation systems, according to various embodiments.

FIG. 3 illustrates a block diagram of a processor core, according to anembodiment.

FIG. 4 illustrates a flow diagram of a method, according to anembodiment.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of various embodiments.However, various embodiments of the invention may be practiced withoutthe specific details. In other instances, well-known methods,procedures, components, and circuits have not been described in detailso as not to obscure the particular embodiments of the invention.Various aspects of embodiments of the invention may be performed usingvarious means, such as integrated semiconductor circuits (“hardware”),computer-readable instructions organized into one or more programs(“software”), or some combination of hardware and software. For thepurposes of this disclosure reference to “logic” shall mean eitherhardware, software, or some combination thereof.

Some of the embodiments discussed herein may provide an efficienttechnique to estimate leakage power (e.g., static or a sub-thresholdleakage power generated by one or more components of an IC device). Inan embodiment, the leakage power consumption may be due to one or morevariations such as variations in temperature and/or voltage (e.g.,threshold and/or supply voltage). Furthermore, some of the embodimentsdiscussed herein may be applied in various computing systems, such asthe computing systems discussed with reference to FIGS. 1, 5, and 6.More particularly, FIG. 1 illustrates a block diagram of a computingsystem 100, according to an embodiment. The system 100 may include oneor more domains 102-1 through 102-M (collectively referred to herein as“domains 102” or “domain 102”). Each of the domains 102-1 through 102-Mmay include various components, but for clarity, sample components areonly shown with reference to domains 102-1 and 102-2. Also, each domain102 may correspond to a portion of a computing system (such as thecomponents discussed with reference to FIGS. 5 and 6, or more generallyto one or more transistors of an IC device). In an embodiment, each ofthe domains 102 may include various circuitry (or logic) that is clockedby a clock signal that may be different than the clock signal used inother domains. In one embodiment, one or more of these clock signals maybe mesosynchronous, or otherwise related (e.g., with a relationship thatmay or may not repeat itself over time).

As illustrated in FIG. 1, each domain may communicate data with otherdomains through one or more buffers 104. In an embodiment, the buffers104 may be first-in, first-out (FIFO) buffers. Each domain may include alogic to estimate leakage power of one or more components within thecorresponding domain (such as logics 106-1 and 106-2 shown withreference to domains 102-1 and 102-2, respectively, and generallyreferred to herein as “logic 106” or “logics 106”), one or moretemperature sensors (such as sensor(s) 108-1 and 108-2 shown withreference to domains 102-1 and 102-2, respectively), a logic to controlfrequency and/or voltage levels and/or provide current threshold voltageand/or supply voltage values (e.g., logics 110-1 and 110-2 shown withreference to domains 102-1 and 102-2, respectively), and a logic tomanage power consumption of one or more components of the correspondingdomain (such as logics 112-1 and 112-2 shown with reference to domains102-1 and 102-2, respectively, and generally referred to herein as“logic 112” or “logics 112”). In an embodiment, the threshold voltage ofa transistor may be adjusted by applying a current to the body (orsubstrate) of the transistor.

In various embodiments, the power management logic 112 may adjust powerconsumption of one or more components of a corresponding domain. Forexample, the logic 112 may utilize information such as the leakage powerestimation value (e.g., provided by the corresponding logic 106),dynamic power estimation, and/or some other information (e.g., committedinstructions per cycle, cache misses, etc.) to adjust supply voltageand/or threshold voltage of one or more components of the correspondingdomain. Also, the logic 112 may adjust the frequency of a clock signal(e.g., a clock signal that is used within at least a portion of thecorresponding domain). In an embodiment, the logic 112 may turn off oneor more components such: one or more processor cores or portions of theprocessor cores (e.g., different pipelines, etc.) and/or data caches(e.g., including various levels of caches such as level 1 (L1), level 2(L2), or other levels) or portions of data caches (e.g., different banksof caches).

FIGS. 2A and 2B illustrate block diagrams of portions of leakage powerestimation systems 200 and 250, according to various embodiments. In oneembodiment, the systems 200 and 250 may be the same or similar to thelogic 106 discussed with reference to FIG. 1. In an embodiment, thestorage units discussed with reference to FIGS. 2A and 2B may be thesame or similar to memory components discussed with reference to FIGS. 5and/or 6.

As shown in FIGS. 2A and 2B, the systems 200 and 250 may include atemperature scaling factor storage unit 202 (e.g., to store a pluralityof temperature scaling factor values). The storage unit(s) 202 mayreceive sensed temperature values from the sensors 108 that correspondto one or more components such as those discussed with reference toFIGS. 1, 5, and 6. The system 200 may also include a voltage scalingfactor storage unit 204 (e.g., to store a plurality of voltage factorvalues) and a reference leakage storage unit 206 (e.g., to store areference or base leakage power value). The base leakage value stored inthe storage unit 206 may be determined at design time (e.g., throughsimulations or circuit measurements) or at test time. For example, thebase leakage value may be determined at test time for designs wherethere is a relatively high variability (since the base value may becalculated independently for each chip and/or block to allow foradapting the estimations to the specifics of each circuit).

In an embodiment, the system 200 may also include a rounding logic 210to round temperature values received from the sensors 108 (e.g., suchthat values sensed may be rounded to a nearest value stored in thestorage unit 202). An interpolation logic 212 may interpolate thevalues, output by the storage unit 202 to actual temperature measurementprovided by the sensors 108. Similarly, the system 200 may include avoltage rounding logic 214 (e.g., to round current threshold and/orsupply voltage values to a nearest value stored in the storage unit 204)and a voltage interpolation logic 218 (e.g., to interpolate the valuesoutput by the storage unit 204 to actual voltage values provided by thecontrol logic 110). A multiplier 208 may multiply the determinedtemperature scaling factor (e.g., looked up from the storage unit 202based on sensed temperature values from sensor(s) 108), the determinedvoltage scaling factor (e.g., looked up from the storage unit 204 basedon current voltage values provided by logic 110), and the referenceleakage value (from the storage unit 206. The multiplication value maythen be utilized to manage power settings (e.g., by the power managementlogic 112) such as discussed with reference to FIG. 1.

Referring to FIG. 2B, the system 250 may include a reference leakagestorage unit 252 that stores base leakage values for a corresponding setof voltages. Accordingly, in one embodiment, a single storage unit (252)may store values that correspond to a combination of values stored inthe reference leakage storage unit 206 of FIG. 2A and correspondingvalues stored in the voltage scaling factor storage 204 of FIG. 2A. Forexample, a plurality of leakage power values may be indexed by atemperature factor (e.g., provided by the sensor(s) 108) and a voltagefactor (e.g., corresponding to the threshold voltage value and/or supplyvoltage value provided by logic 110). Such an embodiment may allow asingle look up (e.g., based on current threshold and/or supply voltagevalues from the logic 110) to provide a reference leakage value that maybe scaled by the temperature scaling factor looked up from the storageunit 202 (e.g., based on sensed temperature value(s) provided by sensors108) via a multiplier 254. Alternatively, the values stored in thestorage units 202, 204, 206, and/or 252 may be combined into a singlestorage unit (not shown) to allow a single look up to provide a leakagevalue that corresponds to sensed temperature value(s) provided bysensors 108 and/or current threshold and/or supply voltage values fromthe logic 110. Also, the system 250 may include rounding and/orinterpolation logic (e.g., that may be the same or similar to the logics210, 212, 214, and/or 218) in accordance with some embodiments.

FIG. 3 illustrates a block diagram of a processor core 300, according toan embodiment. In one embodiment, the core 300 may represent variouscomponents that may be present in a processor or number of processors(such as those discussed with reference to FIGS. 5 and 6). The processorcore 300 may include one or more domains such as a second level cachedomain 302, a frontend domain 304, and one or more backend domains 306.Components within each of the domains 302, 304, and 306 may be clockedby a different clock signal such as discussed with reference to FIG. 1.Moreover, each of the domains (e.g., 302, 304, and 306) may include moreor less components than those shown in FIG. 3 in various embodiments.

The second level (L2) cache domain 302 may include an L2 cache 308(e.g., to store data including instructions), the sensor(s) 108, andlogics 106, 110, and 112. In one embodiment, the L2 cache 308 may beshared by multiple cores in a multi-core processor such as thosediscussed with reference to FIGS. 5 and 6. Also, the L2 cache 308 may beoff of the same die as the processor cores. Accordingly, in variousembodiments of the invention, a processor may include the domains 304and 306, and may or may not include the L2 cache 308.

As shown in FIG. 3, the frontend domain 304 may include one or more ofthe sensor(s) 108, logics 106, 110, and 112, a reorder buffer 318, arename and steer unit 320, a instruction cache 322, a decode unit 324, asequencer 326, and/or a branch prediction unit 328. In one embodiment,the frontend domain 304 may include other components such as aninstruction fetch unit.

The backend domains 306 may include one or more of a first level (L1)cache domain 328 and one or more execution domains 330-1 through 330-N.The L1 cache domain 328 may include an L1 cache 332 (e.g., to store dataincluding instructions), the sensor(s) 108, and logics 106, 110, and112. Furthermore, the execution domains 330-1 through 330-N may includeone or more of an integer execution unit and/or a floating pointexecution unit. The execution domains 330-1 through 330-N may eachcomprise an issue queue (338-1 through 338-N, respectively), a registerfile (340-1 through 340-N, respectively), the sensor(s) 108, logics 106,110, and 112, and/or an execution unit (346-1 through 346-N,respectively).

In one embodiment, each of the domains 302, 304, and 306 may include oneor more first-in, first-out (FIFO) buffer(s) 348 to synchronizecommunication between the various clock domains (e.g., between thedomains 302, 304, and/or 306).

Additionally, the processor core 300 (and, in an embodiment, such as theone shown in FIG. 3, the backend domains 306) may include aninterconnection or bus 350 to facilitate communication between variouscomponents of the processor core 300. For example, after an instructionis successfully executed (e.g., by the execution domains 330-1 through330-N), the instruction commit may be communicated to the ROB 318 (e.g.,via the interconnection 350) to retire that instruction. Additionally,the domains within the backend (e.g., domains 328 and 330-1 through330-N) may communicate via the interconnection 350. For example,communication among execution units (330-1 through 330-N) may occur fortype conversion instructions. Further operations of components of FIGS.1-3 will be discussed with reference to the method 400 of FIG. 4.

Furthermore, even though FIG. 3 illustrates that each of the domains302, 304, and 306 may include the sensor(s) 108 and logics 106, 110, and112, various domains may share the same the sensor(s) 108 and logics106, 110, and 112. For example, a single set of the sensor(s) 108 andlogics 106, 110, and 112 may be utilized for all domains of theprocessor core 300.

FIG. 4 illustrates a flow diagram of a method 400 to provide estimateleakage power, according to an embodiment. In one embodiment, theoperations of the method 400 may be performed by one or more components,such as the components discussed with reference to FIGS. 1-3 and 5-6.

Referring to FIGS. 1-4, at an operation 402, the sensor(s) 108 may senseone or more temperature values corresponding to an IC device. The sensedtemperature value(s) may be used to determine a temperature scalingfactor (e.g., from the storage unit 202) at an operation 404. Atoperation 404, a voltage scaling factor may also be determined such asdiscussed with reference to FIGS. 2A and 2B (e.g., from the storageunits 204 and/or 252). At an operation 406, the determined scalingfactors of operation 404 may then be used to scale a base leakage value(e.g., stored in the unit 206 and/or 252) such as discussed withreference to FIGS. 2A and 2B. At an operation 408, a signal may begenerated (e.g., by the multipliers 205 and 254) that correspond to anestimated leakage power of the IC device. As discussed with reference toFIG. 1, the estimated leakage power (408) may be used to adjust powerconsumption of one or more components of a computing system (e.g.,systems discussed with reference to FIGS. 1, 5, and/or 6).

In an embodiment, the following equation may be used to provide theestimate leakage power at operation 408:

${P\left( {V_{dd},V_{th},T} \right)} = {P_{0} \cdot \frac{V_{dd}}{V_{{dd}\; 0}} \cdot {\mathbb{e}}^{\beta{({V_{dd} - V_{{dd}\; 0}})}} \cdot {\mathbb{e}}^{\gamma \cdot {({{- {V_{th}}} + {V_{{th}\; 0}}})}} \cdot {\mathbb{e}}^{\delta{({T - T_{0}})}}}$

In the above formula, P corresponds to the estimate leakage power value,P₀ corresponds to the base leakage power value (e.g., that may be storedin units 206 and/or 252), V_(dd) corresponds to supply voltage (that maybe provided by the logic 110), V_(th) corresponds to threshold voltage(that may be provided by the logic 110), V_(dd0) corresponds to V_(dd)at which base leakage was measured, V_(tho) corresponds to V_(th) atwhich base leakage was measured, T corresponds to current temperaturevalue(s) sensed by the sensor(s) 108, T₀ corresponds to the temperatureat which base leakage was measured, δ, β and γ are circuit dependentconstants set by the designer. In various embodiments, valuescorresponding to term T(T)=e^(δ·(T-T) ⁰ ⁾ may be stored in the storageunit 202 and values corresponding to the term

${V\left( {V_{dd},V_{th}} \right)} = {\frac{V_{dd}}{V_{{dd}\; 0}} \cdot {\mathbb{e}}^{\beta{({V_{dd} - V_{{dd}\; 0}})}} \cdot {\mathbb{e}}^{\gamma \cdot {({{- {V_{th}}} + {V_{{th}\; 0}}})}}}$may be stored in the storage units 204 (or 252). Hence, a multiplier(208, 254) may be used to multiply the terms T(T) and V(V_(dd), V_(th))to provide value of P.

Moreover, in one embodiment, dynamic calibration of an IC component maybe performed in idle mode (e.g., where there is no dynamic powerconsumption). In such situation, the temperature increase (over acontrolled ambient temperature) in each portion (e.g., blocks) of the ICcomponent may be dependant upon the leakage power. The thermal sensors108 that may be placed in the blocks can report the stable temperature(e.g., after a relatively long period of time). With the temperaturemap, a tool (such as a computing device that is external to the ICcomponent) may derive the power map that is causing the scenario, e.g.,via reverse-engineering. The leakage values may then be computed basedon the static temperatures of the portions (since other constants may beknown, such as supply voltage, threshold voltage, and ambienttemperature), Once the power map is computed it may be stored in thereference leakage storage 206. In an embodiment, a special dedicatedmicrocode may be used to communicate between the IC component beingcalibrated and test equipment (e.g., to report the temperature readingsand to perform the base leakage update).

FIG. 5 illustrates a block diagram of a computing system 500 inaccordance with an embodiment of the invention. The computing system 500may include one or more central processing unit(s) (CPUs) 502 orprocessors that communicate via an interconnection network (or bus) 504.The processors 502 may be any type of a processor such as a generalpurpose processor, a network processor (that processes data communicatedover a computer network 503), or other types of a processor (including areduced instruction set computer (RISC) processor or a complexinstruction set computer (CISC)). Moreover, the processors 502 may havea single or multiple core design. The processors 502 with a multiplecore design may integrate different types of processor cores on the sameintegrated circuit (IC) die. Also, the processors 502 with a multiplecore design may be implemented as symmetrical or asymmetricalmultiprocessors. In an embodiment, one or more of the processors 502 mayutilize the embodiments discussed with reference to FIGS. 1-4. Forexample, one or more of the processors 502 may include one or moreprocessor cores (300). Also, the operations discussed with reference toFIGS. 1-4 may be performed by one or more components of the system 500.

A chipset 506 may also communicate with the interconnection network 504.The chipset 506 may include a memory control hub (MCH) 508. The MCH 508may include a memory controller 510 that communicates with a memory 512.The memory 512 may store data and sequences of instructions that areexecuted by the CPU 502, or any other device included in the computingsystem 500. In one embodiment of the invention, the memory 512 mayinclude one or more volatile storage (or memory) devices such as randomaccess memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM),static RAM (SRAM), or the like. Nonvolatile memory may also be utilizedsuch as a hard disk. Additional devices may communicate via theinterconnection network 504, such as multiple CPUs and/or multiplesystem memories.

The MCH 508 may also include a graphics interface 514 that communicateswith a graphics accelerator 516. In one embodiment of the invention, thegraphics interface 514 may communicate with the graphics accelerator 516via an accelerated graphics port (AGP). In an embodiment of theinvention, a display (such as a flat panel display) may communicate withthe graphics interface 514 through, for example, a signal converter thattranslates a digital representation of an image stored in a storagedevice such as video memory or system memory into display signals thatare interpreted and displayed by the display. The display signalsproduced by the display device may pass through various control devicesbefore being interpreted by and subsequently displayed on the display.

A hub interface 518 may allow the MCH 508 to communicate with aninput/output control hub (ICH) 520. The ICH 520 may provide an interfaceto I/O devices that communicate with components of the computing system500. The ICH 520 may communicate with a bus 522 through a peripheralbridge (or controller) 524, such as a peripheral component interconnect(PCI) bridge, a universal serial bus (USB) controller, or the like. Thebridge 524 may provide a data path between the CPU 502 and peripheraldevices. Other types of topologies may be utilized. Also, multiple busesmay communicate with the ICH 520, e.g., through multiple bridges orcontrollers. Moreover, other peripherals in communication with the ICH520 may include, in various embodiments of the invention, integrateddrive electronics (IDE) or small computer system interface (SCSI) harddrive(s), USB port(s), a keyboard, a mouse, parallel port(s), serialport(s), floppy disk drive(s), digital output support (e.g., digitalvideo interface (DVI)), or the like.

The bus 522 may communicate with an audio device 526, one or more diskdrive(s) 528, and a network interface device 530 (which communicateswith the computer network 503). Other devices may be in communicationwith the bus 522. Also, various components (such as the networkinterface device 530) may be in communication with the MCH 508 in someembodiments of the invention. In addition, the processor 502 and the MCH508 may be combined to form a single chip. Furthermore, the graphicsaccelerator 516 may be included within the MCH 508 in other embodimentsof the invention.

Furthermore, the computing system 500 may include volatile and/ornonvolatile memory (or storage). For example, nonvolatile memory mayinclude one or more of the following: read-only memory (ROM),programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM(EEPROM), a disk drive (e.g., 528), a floppy disk, a compact disk ROM(CD-ROM), a digital versatile disk (DVD), flash memory, amagneto-optical disk, or other types of nonvolatile machine-readablemedia capable of storing electronic instructions and/or data.

FIG. 6 illustrates a computing system 600 that is arranged in apoint-to-point (PtP) configuration, according to an embodiment of theinvention. In particular, FIG. 6 shows a system where processors,memory, and input/output devices are interconnected by a number ofpoint-to-point interfaces. The operations discussed with reference toFIGS. 1-5 may be performed by one or more components of the system 600.

As illustrated in FIG. 6, the system 600 may include several processors,of which only two, processors 602 and 604 are shown for clarity. Theprocessors 602 and 604 may each include a local memory controller hub(MCH) 606 and 608 to allow communication with memories 610 and 612. Thememories 610 and/or 612 may store various data such as those discussedwith reference to the memory 512.

The processors 602 and 604 may be any type of a processor such as thosediscussed with reference to the processors 502 of FIG. 5. The processors602 and 604 may exchange data via a point-to-point (PtP) interface 614using PtP interface circuits 616 and 618, respectively. The processors602 and 604 may each exchange data with a chipset 620 via individual PtPinterfaces 622 and 624 using point to point interface circuits 626, 628,630, and 632. The chipset 620 may also exchange data with ahigh-performance graphics circuit 634 via a high-performance graphicsinterface 636, using a PtP interface circuit 637.

At least one embodiment of the invention may be provided within theprocessors 602 and 604. For example, one or more of the domains 102discussed with reference to FIG. 1 and/or processor core(s) 300 may belocated within the processors 602 and 604. Other embodiments of theinvention, however, may exist in other circuits, logic units, or deviceswithin the system 600 of FIG. 6. Furthermore, other embodiments of theinvention may be distributed throughout several circuits, logic units,or devices illustrated in FIG. 6.

The chipset 620 may communicate with a bus 640 using a PtP interfacecircuit 641. The bus 640 may have one or more devices that communicatewith it, such as a bus bridge 642 and I/O devices 643. Via a bus 644,the bus bridge 643 may be in communication with other devices such as akeyboard/mouse 645, communication devices 646 (such as modems, networkinterface devices, etc. that may be in communication with the computernetwork 503), audio I/O device, and/or a data storage device 648. Thedata storage device 648 may store code 649 that may be executed by theprocessors 602 and/or 604.

In various embodiments of the invention, the operations discussedherein, e.g., with reference to FIGS. 1-6, may be implemented byhardware (e.g., circuitry), software, firmware, microcode, orcombinations thereof, which may be provided as a computer programproduct, e.g., including a machine-readable or computer-readable mediumhaving stored thereon instructions (or software procedures) used toprogram a computer to perform a process discussed herein. Also, the term“logic” may include, by way of example, software, hardware, orcombinations of software and hardware. The machine-readable medium mayinclude a storage device such as those discussed with respect to FIGS.1-6. Additionally, such computer-readable media may be downloaded as acomputer program product, wherein the program may be transferred from aremote computer (e.g., a server) to a requesting computer (e.g., aclient) by way of data signals embodied in a carrier wave or otherpropagation medium via a communication link (e.g., a bus, a modem, or anetwork connection). Accordingly, herein, a carrier wave shall beregarded as comprising a machine-readable medium.

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment may be included in at least animplementation. The appearances of the phrase “in one embodiment” invarious places in the specification may or may not be all referring tothe same embodiment.

Also, in the description and claims, the terms “coupled” and“connected,” along with their derivatives, may be used. In someembodiments of the invention, “connected” may be used to indicate thattwo or more elements are in direct physical or electrical contact witheach other. “Coupled” may mean that two or more elements are in directphysical or electrical contact. However, “coupled” may also mean thattwo or more elements may not be in direct contact with each other, butmay still cooperate or interact with each other.

Thus, although embodiments of the invention have been described inlanguage specific to structural features and/or methodological acts, itis to be understood that claimed subject matter may not be limited tothe specific features or acts described. Rather, the specific featuresand acts are disclosed as sample forms of implementing the claimedsubject matter.

1. An apparatus comprising: a first logic circuitry to generate a firstsignal corresponding to one or more sensed temperature values; and asecond logic circuitry to generate a second signal corresponding to oneor more voltage values; a third logic circuitry to generate a thirdsignal corresponding to a leakage power value based on the first signaland the second signal, wherein the one or more voltage values are tocomprise a current value of a threshold voltage and a current value of asupply voltage; and a fourth logic to generate a fourth signalcorresponding to a base leakage power value, wherein the third logicgenerates the third signal based on the first signal, the second signal,and the fourth signal.
 2. The apparatus of claim 1, further comprising afifth logic to adjust power consumption of one or more components of acomputing system based on the third signal.
 3. The apparatus of claim 1,wherein the leakage power value corresponds to leakage power consumed bya device to which the sensed temperature values and the one or morevoltage values correspond.
 4. The apparatus of claim 1, furthercomprising a storage unit to store a plurality of temperature values,wherein the first logic generates the first signal based on one of theplurality of stored temperature values.
 5. The apparatus of claim 1,further comprising a storage unit to store a plurality of voltagevalues, wherein the second logic generates the second signal based onone of the plurality of stored voltage values.
 6. The apparatus of claim1, further comprising a storage unit to store a plurality of leakagepower values, wherein the plurality of leakage power values are indexedby the temperature and the voltage.
 7. The apparatus of claim 1, furthercomprising one or more temperature sensors to sense the temperaturevalues.
 8. The apparatus of claim 1, wherein the third logic comprises amultiplier to multiply the first and second signals to provide the thirdsignal.
 9. The apparatus of claim 1, further comprising one or moreprocessor cores, wherein at least one of the one or more processor corescomprises one or more of the first logic, the second logic, or the thirdlogic.
 10. The apparatus of claim 1, further comprising one or moreprocessor cores, wherein at least one of the one or more processorcores, the first logic, the second logic, and the third logic are on asame die.
 11. A method comprising: determining a temperature scalingvalue corresponding to one or more temperature values sensed from adevice; determining a voltage scaling value based on one or more voltagevalues corresponding to the device; and scaling a reference leakagepower value of the device based on a base leakage power value, thetemperature scaling value and the voltage scaling value to generate asignal corresponding to a leakage power of the device, wherein the oneor more voltage values are to comprise a current value of a thresholdvoltage and a current value of a supply voltage.
 12. The method of claim11, wherein the sensing and scaling are performed during run-time of thedevice.
 13. The method of claim 11, wherein determining the temperaturescaling value comprises accessing a storage unit.
 14. The method ofclaim 11, wherein determining the voltage scaling value comprisesaccessing a storage unit.
 15. The method of claim 11, wherein scalingthe reference leakage power value comprises multiplying the referenceleakage power value by the temperature and voltage scaling values. 16.The method of claim 11, further comprising determining the referenceleakage power value during test or design of the device.
 17. A computingsystem comprising: a memory to store a plurality of bits representing aplurality of scaling factors; a first logic having one or morecomponents to perform one or more computing operations; and a secondlogic to scale a base leakage power value corresponding to at least oneof the one or more components based, at least in part, on sensedtemperature variations and one or more of the plurality of storedscaling factors, wherein at least one of the plurality of stored scalingfactors corresponds to a current value of a threshold voltage and acurrent value of a supply voltage, wherein the second logic is tocomprise a multiplier to multiply a first signal corresponding to atemperature scaling value, a second signal corresponding to a voltagescaling value, and a third signal corresponding to the base leakagepower value.
 18. The computing system of claim 17, further comprising athird logic to adjust power consumption of at least one of the one ormore components based on the scaled leakage power value.
 19. Thecomputing system of claim 17, wherein at least one of the plurality ofstored scaling factors corresponds to a voltage scaling value.
 20. Thecomputing system of claim 19, wherein the voltage scaling valuecorresponds to one or more voltage values.
 21. The computing system ofclaim 20, wherein the one or more voltage values comprise the currentvalue of a threshold voltage and the current value of a supply voltage.22. The computing system of claim 17, wherein the plurality of thestored scaling factors comprises a plurality of temperature scalingvalues and a plurality of voltage scaling values.
 23. The computingsystem of claim 17, wherein the memory comprises a read-only memory. 24.The computing system of claim 17, further comprising one or moreprocessor cores, wherein at least one of the one or more processor corescomprises one or more of the first logic, the second logic, or thememory.
 25. The computing system of claim 17, further comprising one ormore processor cores, wherein at least one of the one or more processorcores, the first logic, the second logic, and the memory are on a samedie.
 26. The computing system of claim 17, wherein the one or morecomputing operations comprise one or more of data processing, datastorage, and data communication.
 27. The computing system of claim 17,further comprising an audio device.
 28. The computing system of claim17, further comprising one or more sensors to sense the temperaturevariations.